DIGITAL SYSTEM DESIGN PROJECT

• Simple RISC Processor Instruction Set Architecture v3.2
• Simple RISC Processor Pipeline v1.0
• Simple RISC Processor Pipeline - Parallel Execution Units
• Simple RISC Processor Minisystem v1.0

1. Simple RISC Processor golden model
2. Macro Usage Guideline
3. Step by step pipeline implementation
4. Step by step parallel implementation
5. Step by step memory controller design

• Verilog Tutorial from ASIC World
• Verilog Tutorial from Chip Verify
• Verilog reference guide
• AXI4 Specification (sections A1, A2, A3.1, A3.2, A3.3, B1)

IDE for FPGA based design (HDL and system design, simulation, synthesis, firmware etc):

• Xilinx: Vivado ML (select WebPACK Edition for free)