Memory Controller step by step design

The memory controller (MemCtrl) talks with the host through the UART block, which is to be an instance of Xilinx LogiCORE UART IP, and enables the host to access the memory of the Simple RISC processor. The memory is an FPGA block memory, whose description should obey one of the templates recommended by Xilinx in order to be synthesized as an instance of a block memory.
Basically, the memory controller reassembles the host data packets from the bytes received through the UART receiver, interpretes the commands from the packets and takes the proper action, which may be either a change of the state of the Simple RISC processor (start, reset, halt) or a data routing for the following received bytes, from UART to the memory, or from the memory to the UART if a read request from the host was received.

1 - design the AXI4 Lite interface that connects to the UART block. The memory controller is the AXI4 master. It sends the read/write addresses and the write data to the UART block, and reieves the read data from it. Each access is atomic - one address + one data word. The only addresses used are the addresses of the UART block registers (see Table 4 from LogiCORE IP spec). The data has 32 bits but only the lowest byte is used.

2 - design the high level protocol used between host and MemCtrl. Basically there are 5 packet types:
      - reset (resets and then stops the Simple RISC PC)
      - halt  (stops the Simple RISC PC)
      - start (enables the Simple RISC PC)
      - write memory from a start address a given number of memory words. The packet contains the command, the start address, the length, and the data payload.
      - read memory from the start address a given number of memory words. The packet contains the command, the start address, and the length. MemCtrl reads from the memory and sends back the required number of memory words.
Think of the changes needed for the Simple RISC processor in order to react to the first 3 commands (reset, halt, start). They need to be as small as possible.

3 - design the MemCtrl FSM. Additional buffers may be needed to assemble/disassemble the data received/transmited from/to the UART block. For example, upon receiving data to write into the memory, the FSM should assemble 4 successive bytes from the UART block into one 32 bits memory word before writing it into the memory. When sending memory data back to the UART block, the FSM splits the read memory word into 4 bytes and sends them one by one to the UART block through the write channel.