Simple RISC Processor Golden Model

I. DEFINITION

- executes one instruction at a time.

- interface:
module seq_core(
    // general
    input 		rst,   // active 0
    input		clk,
    // program memory
    output [A_SIZE-1:0] pc,
    input        [15:0] instruction,
    // data memory
    output 		read,  // active 1
    output 		write, // active 1
    output [A_SIZE-1:0]	address,
    input  [D_SIZE-1:0]	data_in,
    output [D_SIZE-1:0]	data_out
);

- reset clears all registers and PC

- instructions have opcode fields defined through macros.
Example:
`define	ADD 7'b0000001

- registers have numerical values defined through macros
Example:
`define R1 3'd1
`define R2 3'd2

- instructions are presented to the core in test files as assembler macros
Example:
instr = {`ADD, `R2, `R1, `R0} // ADD R2 R1 R0

- memory address is taken from the lower A_BITS of the register given as address operand.

II. ASSIGNMENTS

- write seq_core module behavioral description;

- write tests to check that each instruction type is properly executed for random operands values;

- write tests for simple sequences of instructions (e.g. the integer multiplication algorithm);

- instructions and data are provided as input stimuli

- you may declare in the test module a vector of instructions, properly initialized,
from which the test selects one instruction using the pc output of seq_core as selection index.

III. ASSUMPTIONS

- floating point instructions are treated as integer instructions

- LOAD instruction takes the current data_in value
as the data value to be saved in the destination register