ADDITIONAL ASSUMPTIONS

A.
Assume a simplified EXF unit, EX(F), that does integer addition/subtraction with integer operands for ADDF and SUBF instructions.
The EX(F) could be another instance of the usual EX execution unit (but without connections for the memory data port).

B.
Emulate the real floating point execution unit latency with four pipeline registers (p1, p2, p3, p4) in front of the EX(F) instance.
Those four pipeline registers are connected in a shift chain that propagates the floating point instruction from the output of the Read stage
to the input of the EX(F) instance in four clock cycles:
READ -> p1 -> p2 -> p3 -> p4 -> EX(F)


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PARALLEL PIPELINE STEP BY STEP DESIGN

1.
Instantiate one more EX module.
Modify the Read stage to be able to dispatch the current instruction to the proper execution unit, assuming no data or control dependencies.
Modify the Write-back stage to be able to select the available result, or the older result if two results are simultaneously available.
Provide the backpressure to the EX and possibly Read and Fetch stages if the EX result could not be selected.
1.a. Test sequence of independent integer arithmetic&logic instructions
1.b. Test sequence of independent floating point arithmetic instructions
1.c. Test sequence of independent mixed floating point arithmetic and integer arithmetic&logic instructions

2.
Modify the module for data dependency control such that it accounts for all possible data forwarding pathways.
Keep in mind that the result of a floating point instruction is available only in the fourth clock cycle of its execution.
2.a. Test sequence of integer arithmetic&logic instructions
2.b. Test sequence of floating point arithmetic instructions
2.c. Test sequence of mixed floating point arithmetic and integer arithmetic&logic instructions

NOTE: Tests 2.x. may be the same as 1.x. but with the distance between instructions shortened until dependency occur
Example test 1.a.1.
ADD R3 R2 R1
ADD R6 R5 R4
NOP
NOP
ADD R7 R6 R3

Example test 2.a.1.
ADD R3 R2 R1
ADD R6 R5 R4
ADD R7 R6 R3

3
Theoretically the logic of the EX execution stage that deals with jump instructions needs only a very small change.
In case the jump instruction must be stalled in the EX stage because of backpressure from Write-back stage,
it is replaced with a NOP in front of the EX execution unit as usual, and is not propagated to the Write-back stage
(it has finished with PC updating, therefore it is no longer needed)
3.a. Test sequence with various jump instructions inserted between mixed floating point arithmetic and integer arithmetic&logic instructions

4.
Modify the Write-back stage such that a stalled LOAD instruction saves internally the data_in value
and forwards the input data_in or the saved data_in value if it's a new LOAd or a stalled LOAD instruction.
4.a. Test sequence of integer arithmetic&logic instructions mixed with LOADs
4.b. Test sequence of floating point arithmetic instructions mixed with LOADs
4.c. Test sequence of mixed floating point arithmetic, integer arithmetic&logic, and LOAD instructions
4.d. Test sequence of mixed floating point arithmetic, integer arithmetic&logic, LOAD, and control instructions