Step by step Floating-Point Unit (FPU) design and verification

1.
Implement the FPU taking into account only the normalized positive numbers.
The design needs only a comparison of exponents, an operand to be shifted for alignment (if needed), and an adder.
Verify the design with different numbers that are not too large or too small.

2.
Add the necessary blocks to handle negative normalized numbers and subtraction.
You need at least one inverter to complement one of the operands,
a priority encoder to get the position of the greatest nonzero bit of the adder's result,
a left shifter for the adder's result, a correction for the result's exponent, and a control block to manage negative numbers and subtractions.

Verify that your design works with the previous numbers, and with various pairs of positive and negative numbets, both for addition and subtraction.

3.
Change or add what is necessary to handle denormalized operands, and to generate a denormalized result if needed.

Verify the design with pairs of inputs for which one or both operands are denormalized,
and with operands whose values are sufficiently close to get a denormalized result.

4.
Add the required logic that recognizes infinite or invalid (NaN) operands, and generates the corresponding result.
This logic must also recognize an overflow from the adder's result to generate an infinite result, positive or negative according to the operands.
If the operands are infinites of opposing signs, the result must be NaN.

Check the functionality with infinite or NaN inputs.