ADDITIONAL ASSUMPTIONS

A.
Assume a simplified EF unit, E(F), that does integer addition/subtraction with integer operands for ADDF and SUBF instructions.
The E(F) could be another instance of the usual E execution unit (but without connections for the memory data port).

B.
Emulate the real floating point execution unit latency with three additional pipeline registers that propagates the result of the E(F) unit.
Also, even if the result of the E(F) unit is available from the first cycle of the execution pipeline,
you should not forward it sooner than the last (4th) cycle of the execution pipeline:
R -> E(F) -> E2 -> E3 -> E4 -> W


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PARALLEL PIPELINE STEP BY STEP DESIGN

1.
Instantiate one more E module.
Modify the Read stage to be able to dispatch the current instruction to the proper execution unit, assuming no data or control dependencies.
Add a second write port to Register file, and connect it to the W stage of the floating-point pipeline.
1.a. Test sequence of independent integer arithmetic&logic instructions
1.b. Test sequence of independent floating point arithmetic instructions
1.c. Test sequence of independent mixed floating point arithmetic and integer arithmetic&logic instructions

2.
Modify the module for RAW data dependency control such that it accounts for all possible data forwarding pathways.
Keep in mind that the result of a floating point instruction is available only in the fourth clock cycle of its execution.
2.a. Test sequence of integer arithmetic&logic instructions
2.b. Test sequence of floating point arithmetic instructions
2.c. Test sequence of mixed floating point arithmetic and integer arithmetic&logic instructions
NOTE: The test sequences may have only RAW dependencies.
NOTE: Tests 2.x. may be the same as 1.x. but with the distance between instructions shortened until the RAW dependency occurs
Example test 1.a.1.
ADD R3 R2 R1
ADD R6 R5 R4
NOP
NOP
ADD R7 R6 R3

Example test 2.a.1.
ADD R3 R2 R1
ADD R6 R5 R4
ADD R7 R6 R3

3.
Add the Instruction Window (IW) and the logic that selects instructions for dispatch based on RAW dependencies and forwarding paths.
Take into account that up to 2 instructions may be dispatched at a time, and each of them may have up to two sources. Therefore, up to 4 operands may be forwarded,
from any of the four forwarding sources (E stage, last stage of EF, W stage from integer pipeline, and W stage from floating-point pipeline)
3.a. Test that newer independent instructions are bypassing older dependent instructions stalled in the IW.

4.
Add in the Read stage the logic that manages WAW dependecy, detecting the WAW dependency of the newest instruction to any other instruction in IW
or in the first 3 stages of the floating-point pipeline, and stalls it and the fetch stage until the WAW dependecy is cleared.
4.a. Test sequences that have RAW and WAW dependencies.

5.
Extend the logic circuit of step 4 to account also for the WAR dependencies that may occur between the newest instruction in IW and any other instruction in IW.
5.a. Test sequences that have all kinds of data dependencies.

6.
Extend the logic circuit of step 5 to handle also control dependencies. The fetch stage should be stalled until the branch instruction is dispatched for execution.
6.a. Arbitrary test sequences.