The Connex Project

The Connex Project started with the Connex Memory.

Connex Memory: is the hardware support for efficient string store, search, insert, read and delete.

The concept of Connex Memory (CM) is a sequel of the Lisp Machine project (see the story in [Stefan '02]). The concept is first presented in [Stefan '85/91], but unpublished until 1991 because "the cabinet 2" has forbidden the use of the sintagm "artificial intelligence".

The main feature of CM consists in searching strings in "constant" time ("constant" instead constant because of a very small weighted log which is inevitably there due to of physical reasons). For example, if the string "george" is to be searched in a very big string, then the following sequence of commands identifies all the occurences of "george" and accesses the first:

find g; cfind e; cfind o; cfind r; cfind g; cfind e;
John Sununu, explaining to Bill Frezza the reasons to invest in Connex Technology, uttered the best explanation for this feature of the Connex Memory:
Using Connex Memory, George searches "the needle in a hay stack" using time proportional with the size of "the needle" rather than time proportional with the size of "the stack".

The main development stages of the concept of CM

1. The initial definition

CM is a sort of associative memory containing a string of variables whose value can be accessed to be read or modified using the following set of simple one cycle operations:

reset s : all the variables after the first marked variable take the value s
find s : all the variables that follow a variable having the value s switch to the marked state and the rest switch to the nonmarked state
cfind s : all the variables that follow a marked variable having the value s switch to the marked state and the rest switch to the nonmarked state
insert s : the value s is inserted before the first marked variable
readup | down | - : the output has the value of the first marked variable and the marker moves one position to right (up) or to left (down) or remains unchanged (-)
delete : the value stored in the first marked position is deleted, the position remains marked (in the current cycle the output has the value of the deleted variable) and the symbols from the right are moved one position left.

For an extended description see [Stefan '98a].

2. Exotic applications

A lot of exotic applications were investigated prior to 2001:

Artificial Life (see [Stefan '95])
Algorithmic Complexity (see [Stefan '96])
Molecular Computing (see [Stefan '97], [Stefan '97a], [Stefan '98b])
Theory of Computation (see [Stefan '98], [Stefan '98a])

The main colaborators: Mihaela Malita and Robert Benea

3. From CM to Connex Engine

In 2001 spring semester, during a sabatical half-year, the concept of CM is applied to bio-informatics and expanded in a colaborative work with Dominique Thiebaut. CM becomes Connex Engine (CE) expanding the physical resources from one-word cell to many-word cells.

The application domain investigated with CE is bioinformatics (see [Stefan '01] and Dominique's research web page).

The main outcome of this stage is the patent application issued in August 2001.

4. The Connex Architecture

In 2001 Fall semester the concept of Connex Architecture (CA) was developed with Dan Tomescu. The CE becomes now a general purpose computational architecture.

The first application investigated by Dan Tomescu using CA: in memory data bases.
The second application investigated was a SoC for still camera. Basic algorithms on CA where developed in colaboration with Mihaela Malita and Dominique Thiebaut.

The prototype version of ConnexArray^TM - an array of 4096 processing elements - was designed and produced at TSMC. Main collaborators: Bogdan Mitu (testing), Victor Radu-Radulescu (physical design).

5. Connex Technology

Starting from 2003 inside Connex Technology, Inc. (co-founded with Paul Conley, John Sununu, Dominique Thiebaut, Dan Tomescu) CA is developed as Connex Technology optimizing CA for a specific application domain: image processing. The main colaborators in this stage are: Bogdan Mitu, Dan Tomescu.

The company has built a PCI board deploying 4 of its ConnexArray^TM test chips, each of which contains 4,096 PEs. The board was used by Government Agencies for string searches of very large databases, utilizing the Connex machine capability to search for a string in a time proportional to the length of the string, rather than the size of the database, as is the case with conventional search engines.

Connex Technology is implemented and patented as the core of CA1024 chip produced by Connex Technology, Inc. (see [Stefan '06] for architectural description and for the basic performances). The new features added in this stage are:

Connex Programming Lannguage (CPL)
"microprogram-like" execution at the Processing Element (PE) level
hardware support for multiplication
hardware support for scalar vector multiplication
Input-Output System

The first public presentation of Connex Technology occurs in Microprocessor Report.

In 2007 company changed its name in BrightScale.

Milestones:

Dec. 2003: CA4096 - the first ever made one-chip having 4096 16-bit PEs on 1cm² (the first prototipe produced at TSMC in 130nm technology)

Febr. 2007: BA1024 - a SoC for the HDTV market, containing CA1024 (a ConnexArray of 1024 PEs) produced at TSMC (90 nm standard process) is the first one chip parallel machine with the following performances:

200 GOPS (Giga 16-bit OPerations per Second)
>60 GOPS/Watt
>2 GOPS/mm²

July 2007: the first real & complex application (HDTV postprocessing) running on BA1024 in Universitatea Politehnica Bucuresti (the software team coordinated by Bogdan Mitu, Marius Stoian, and Radu Weiss)

March 2008: BA1024B - a SoC for the HDTV market, containing CA1024 (a ConnexArray of 1024 PEs) produced at TSMC (65 nm standard process) with the following performances:

400 GOPS (Giga 16-bit OPerations per Second)
>120 GOPS/Watt
>6.25 GOPS/mm²

January 2009: BrightScale turned Out the lights: "We worked this one really hard," said Bill Frezza, a general partner at Adams Capital Management who held a board seat at the Sunnyvale, Calif.-based company. "This was a long, hard investment. We just came to the end of our rope." (quoted from "The Wall Streret Journal", May 14, 2009)

6. NeoConnex Approach: the pRISC accelerator in a heterogenous computing system

Collaborators: Mihai Antonescu, Calin Bira, Radu Hobincu, Mihaela Malita, George-Vladut Popescu, Marius Stoian, Vlad Serbu, Costin-Emanuel Vasile.

Theoretical investigations:

Main collaborator: Mihaela Malita
Main result: MapScanReduce abstract model for parallel computing based on Stephen Kleene's mathematical model of partial recursive functions.

Hardware adds:

Main collaborators: Mihai Antonescu, George-Vladut Popescu
pRISC: a parametrized and configurable versioon of the abstract model MapScanReduce
Main new features:

data transfer transperent to the processing
transfer unit with in flight data rearangement
floating-point arithmetic
multi-function scan loop

Software stack (developing):

Coordinator: Marius Stoian
Contributors: Mihai Antonescu, George-Vladut Popescu, Vlad Serbu
Main components: (SDK_IDE (Assembler Debugger Profiler Tuner) XRT (Simulator GoldenModel XilinxBoard))

Test assembly code:

Main collaborators: Mihai Antonescu, Mihaela Malita, George-Vladut Popescu
Data transfer functions, Linear algebra functions, Signal processing functions, Protein folding, Graph operations, Encription, ...
Matrix multiplication perfromances in Machine Learning domain for 1024 x 1024 matricces with p execution units:

Architectural perfromance: 6p times less the execution time compared to mono-core performance
Energy use: 10 times less for the same amount of computation compared with general purpose GPUs
Area use: 3 times less for the same amount of computation compared with general purpose GPUs

First target: ONNX

Managerial activities

Calin Bira

For details see: "X3PU General Purpose Parallel Processing Unit used as Accelerator in a Heterogenous Computing System"

References

Patents:

Gheorghe Stefan, Dominique Thiebaut: Memory Engine for the Inspection and Manipulation of Data (United States Patent 6,760,821, February 20, 2003; Filed: August 10, 2001)
Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu: Associative memory device (United States Patent 7,069,386, June 27, 2006; Filed: May 10, 2004)
Dan Tomescu, Gheorghe Stefan: Data processing system having a Cartesian Controller (United States Patent 7,107,478, September 12, 2006; Filed: December 4, 2003)
Gheorghe Stefan, Dan Tomescu: Cellular Engine for a Data Processing System, (United States Patent 7,383,421, June 3, 2008 ; Filed: December 4, 2003)
Bogdan Mitu, Gheorghe Stefan, Dan Tomescu: Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing, (United States Patent 7,451,293, November 11, 2008 ; Filed: Oct. 21, 2005,)
Gheorghe Stefan, Dan Tomescu: Cellular Engine for a Data Processing System, (United States Patent 7,908,461, March 15, 2011 ; Filed: December 19, 2007)
Bogdan Mitu, Lazar Bivolarski, Gheorghe Stefan: System and method for class-based execution of an instruction broadcasted to an array of processing elements (United States Patent 9,563,433, February 7, 2017 ; Filed: December 18, 2012)

Publications:

[Stefan '85/91] Gh. Stefan, V. Bistriceanu, A. Paun, "Catre un mod natural de implementare a LISP-ului" (Toward a Natural Way to Implement LISP), in Sisteme cu inteligenta artificiala (Systems for Artificial Intelligence), Ed. Academiei Romane, Bucuresti, 1991 (paper at Al doilea simpozion national de inteligenta artificiala (The Second National Symposium on Artificial Intelligence), Sept. 1985). p. 218 - 224.
[Stefan '86] Gh. Stefan, "Memorie conexa" (The Connex Memory) in CNETAC 1986 Vol. 2, IPB, Bucuresti, 1986, p. 79 - 81.
[Stefan '91] Gh. Stefan, F. Draghici, "Memory Management Unit - a New Principle for LRU Implementation" in Proceedings of 6th Mediterranean Electrotechnical Conference, Ljubljana, Yugoslavia, May 1991. p. 989 - 992.
[Stefan '91a] Gh. Stefan, F. Draghici, "Memory Management Unit with a Performant LRU Circuit" in Buletinul IPB, Tom LIII, Nr. 1-2, 1991. p. 89 -96.
[Stefan '95] Gh. Stefan, Mihaela Malita, "The Eco-Chip: A Physical Support for Artificial Life Systems", in Artificial Life. Grammatical Models, ed. by Gh. Paun, Black Sea University Press, Bucharest, 1995. p. 260 - 275.
[Hascsi '95a] Z. Hascsi, Gh. Stefan, "The Connex Content Addressable Memory (C2AM)" in Proceedings ot the Twenty-first European Solid-State Circuits Conference, Lille - France, 19 - 21 Sept. 1995, p.422-425.
[Stefan '96] Gh. Stefan, Mihaela Malita, "Chaitin's Toylisp on a Connex Memory Machine", in Journal of Universal Computer Science, Vol. 2, No. 5, May 28, 1996, p.410 - 426. (Special Issue: C. Calude (ed.): The Finite the Unbounded and the Infinite, Proceedings of the Summer School "Chaitin,s Complexity and Applications", 27 June - 6 July, 1995.)
[Hascsi '96a] Z. Hascsi, B. Mitu, M. Petre, G. Stefan, "High-Level Synthesis of an Enchanced Connex memory", in Proceedings of the International Semiconductor Conference, Sinaia, October 1996, p. 163-166.
[Stefan '97] Gh. Stefan, Mihaela Malita, "DNA Computing with the Connex Memory", in RECOMB 97 First International Conference on Computational Molecular Biology, January 20 - 23, Santa Fe, New Mexico, 1997. p. 97-98.
[Stefan '97a] Gh. Stefan, Mihaela Malita, "The Splicing Mechanism and the Connex Memory", Proceedings of the 1997 IEEE International Conference on Evolutionary Computation, Indianapolis, April 13 -16, 1997. p. 225-229.
[Stefan '98] Gh. Stefan, Robert Benea, "Connex Memories & Rewriting Systems", in MELECON '98 9th Mediterranean Electrotechnical Conference, May 18-20, 1998, Tel-Aviv, Israel. p 1299-1303.
[Stefan '98a] Gh. Stefan, "The Connex Memory: A Physical Support for Tree / List Processing", in The Roumanian Journal of Information Science and Technology, Vol.1, Number 1, 1998, p. 85 - 104.
[Stefan '98b] Gh. Stefan, "Silicon or Molecules? What's the Best for Splicing", in Gh.Paun (ed.) Computing with Bio-Molecules. Theory and Experiments, in Springer, 1998. p. 158-181
[Stefan '01] Gh. Stefan, Dominique Thiebaut, "Hardware-Assisted String-Matching Algorithms", in WABI 2001, 1st Workshop on Algorithms in BioInformatics, BRICS, University of Aarhaus, Danemark, August 28-31, 2001.
[Thiebaut '02] D Thiebaut, G Stefan: Ziv-Lempel compression with the Connex Engine - 2002 https://www.researchgate.net/profile/Dominique_Thiebaut/publication/248495744_Ziv-Lempel_compression_with_the_Connex_Engine/links/53f2103f0cf2bc0c40e705c7.pdf
[Stefan '02] G. Stefan: "Masina DIALISP - o realizare cu efecte intarziate", in Computers and Computer Networks in Romania 1953-1985, Romanian Academy, 11/22/2001.
[Stefan '06] G. Stefan: "The CA1024: A Massively Parallel Processor for Cost-Effective HDTV", in SPRING PROCESSOR FORUM: Power-Efficient Design, May 15-17, 2006, Doubletree Hotel, San Jose, CA.
[Stefan1 '06] G. Stefan: "The CA1024: A Massively Parallel Processor for Cost-Effective HDTV", in SPRING PROCESSOR FORUM: Power-Efficient Design, June 8-9, 2006, Tokyo
[Malita '06] Mihaela Malita, Gheorghe Stefan, Marius Stoian: "Complex vs. Intensive in Parallel Computation", in International Multi-Conference on Computing in the Global Information Technology - Challenges for the Next Generation of IT&C - ICCGI 2006 Bucharest, Romania, August 1-3, 2006.
[Thiebaut '06] Dominique Thiebaut, Gheorghe Stefan, Mihaela Malita: "DNA search and the Connex technology" in International Multi-Conference on Computing in the Global Information Technology - Challenges for the Next Generation of IT&C - ICCGI 2006 Bucharest, Romania, August 1-3, 2006.
[Stefan2 '06] Gheorghe Stefan, Anand Sheel, Bogdan Mitu, Tom Thomson, Dan Tomescu: "The CA1024: A Fully Programable System-On-Chip for Cost-Effective HDTV Media Processing", in Hot Chips: A Symposium on High Performance Chips, Memorial Auditorium, Stanford University, August 20 to 22, 2006.
[Stefan3 '06] Gheorghe Stefan: "The CA1024: SoC with Integral Parallel Architecture for HDTV Processing", invited paper at 4th International System-on-Chip (SoC) Conference & Exhibit, Radisson Hotel Newport Beach, CA, November 1 & 2, 2006.
[Stefan4 '06] Gheorghe Stefan: "Integral Parallel Computation", in Proceedings of the Romanian Academy, Series A: Mathematics, Physics, Technical Sciences, Information Science, vol. 7, no. 3 Sept-Dec 2006, p.233-240.
[Malita '07] Mihaela Malita, Gheorghe Stefan, Dominique Thiebaut: "Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation" in ACM SIGARCH Computer Architecture News, Volume 35 , Issue 5, Dec. 2007, Special issue: ALPS '07 - Advanced low power systems; communication at International Workshop on Advanced Low Power Systems held in conjunction with 21st International Conference on Supercomputing June 17, 2007 Seattle, WA, USA.
[Malita1 '07] Mihaela Malita, Gheorghe Stefan: "Membrane Computing in Connex Environment", in G. Eleftherakis, P. Kefalas, Gh. Paun, G. Rozenberg, A. Saloma (Eds.): Membrane Comoputing, Springer-Verlag, 2007.
[Malita '08] Mihaela Malita, Gheorghe Stefan: "On the Many-Processor Paradigm", in: H. R. Arabina (Ed.): Proceedings of the 2008 World Congress in Computer Science, Computer Engineering and Applied Computing, vol. PDPTA'08 (The 2008 International Conference on Parallel and Distributed Processing Techniques and Applications), 2008.
[Stefan '09] Gheorghe Stefan: "One-Chip TeraArchitecture", in Proceedings of the 8th Applications and Principles of Information Science Conference, Okinawa, Japan on 11-12 January 2009.
[Mitu '09] Bogdan Mitu, Gheorghe M. Stefan: Stereo Vision for Automotive Industry on Connex Architecture, DCAE-ETTI Research report, 2009.
[Malita '09] Mihaela Malita, Gheorghe Stefan: "Integral Parallel Architecture & Berkeley's Motifs", in ASAP09 - 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 7-9 July, 2009, Boston, MA, USA, pag. 191-194. DOI: 10.1109/ASAP.2009.40
[Malita1 '09] Mihaela Malita, Gheorghe Stefan: "The Berkeley Motifs and an Integral Parallel Architecture", in ROMJIST, vol. 12, no. 1, 2009, pag. 35-49
[Stefan '09] Gheorghe Stefan, Bogdan Mitu, Marius-Ciprian Stoian: "Heterogeneous vs. Homogeneous in Integral Parallel Computation", in vol. Scoala de microelectronica. Volum de lucrari dedicate profesorului acad. Mihai Draganescu cu ocazia aniversarii varstei de 80 ani, Ed. Rosetti Educational, 2009, pag. 114-132.
[Stefan '10] Gheorghe Stefan: "Integral Parallel Architecture in System-on-Chip Designs", in The 6th International Workshop on Unique Chips and Systems, Atlanta, GA, USA, December 4, 2010, pag. 23-26.
[Bumbacea '10] Petronela Bumbacea, Valeriu Codreanu, Radu Hobincu, Lucian Petrica, Gheorghe M. Stefan: "Technology Driven Architecture for Integral Parallel Embedded Computing", in CAS 2010 Proceedings, vol.1, pag.35-42.
[Calfa '10] Ana-Maria Calfa, Gheorghe Stefan: "Matrix Computation on the Connex Parallel Architecture", International Conference on Signals and Electronic Systems, Gliwice, Poland, Sept. 2010.
[Malita '10]Mihaela Malita, Gheorghe Stefan: "Many-Processor & Kleene's Model", in Scientific Buletin of UPB, serie C, no. 3, 2010, pag. 199-212.
[Lorentz '10] I. Lorentz, M. Malita, R. Andonie: "Fitting FFT onto an Energy Efficient Massively Parallel Architecture", in The Second International Forum on Next Generation Multicore/ Manycore Technologies, June, 2010.
[Lorentz '11] Istvan Lorentz, Mihaela Malita, Razvan Andonie: "Evolutionary Computation on the Connex Architecture", in The 22nd Midwest Artificial Intelligence and Cognitive Science Conference, Cincinnati, Ohio, 2011.
[Malita '11] Mihaela Malita, Gheorghe M. Stefan: "Parallel RISC Architecture. A Functional Approach Based on Backus's FP language", in The 2011 International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, 2011.
[Malita1 '11] Mihaela Malita, Gheorghe M. Stefan: "Backus Language for Functional Nano-Devices", in CAS 2011, Sinaia, Oct. 2011, vol. 2 pp. 331-334.
[Malita '12] Mihaela Malita, Gheorghe M. Stefan: "Architectural Principles for One-Chip Parallel Computer", in Recent Advances in Information Science. Proceedings of the 3rd European Conference of Computer Science, Paris, France, December 2-4, 2012, pp 143-148.
[Stefan '12] Gheorghe M. Stefan: "Cyber-Physical Society - iDemocracy" in Journal of Control Engineering and Applied Informatics, Vol.14, No.3, pp. 54-60 , 2012.
[Bira '13] Calin Bira, Liviu Gugu, Mihaela Malita, Gheorghe M. Stefan: "Maximizing the SIMD Behavior in SPMD Engines", in Proceedings of the World Congress on Engineering and Computer Science 2013 Vol I WCECS 2013, 23-25 October, 2013, San Francisco, USA, pp 156-161. ISBN: 978-988-19252-3-7 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online) at: http://www.iaeng.org/publication/WCECS2013/WCECS2013_pp156-161.pdf
Calfa'13] Ana-Maria Calfa, Gheorghe STEFAN: Matrix Inverse on Connex Parallel Architecture in U.P.B. Sci. Bull., Series C, Vol. 75, Iss. 2, pp. 91-100, 2013. ISSN 1454234X
[Stefan '14] Gheorghe M. Stefan, Mihaela Malita: "Can One-Chip Parallel Computing Be Liberated From Ad Hoc Solutions? A Computation Model Based Approach and Its Implementation", 18th International Conference on Circuits, Systems, Communications and Computers (CSCC 2014), Santorini Island, Greece, July 17-21, 2014, 582-597. ISBN: 978-1-61804-237-8 in ISSN: 1790-5109 ISBN: 978-1-61804-236-1 at: http://www.inase.org/library/2014/santorini/COMPUTERS1.pdf
[Bira '14] Calin Bira, Liviu Gugu, Mihaela Malita, Gheorghe M. Stefan: "Transpose-MapReduce Applications on Connex Architecture", in ROMJIST, Volume 17, Number 2, 2014, pp. 150–176.
[Stefan1 '14] Gheorghe M. Stefan: "MapReduce - an Integrative Paradigm in Cyber-Physical Systems" in Proceedings of The Third International Workshop on Cyber-Physical Systems, May 2014.
[Malita '15] Mihaela Malita, Gheorghe M. Stefan: "From Kleene's Model to the Parallel Abstract Machine" (unpublished)
[Malita1 '15] Mihaela Malita, Gheorghe M. Stefan: "MapReduce Programmable Accelerator for Neural Networks", ICAT 2015, Antalya, Aug., 2015. pp. 359-363 ISBN: 978-605-9119-26-9 Proceedings at: http://www.icat15.icatsconf.org/proceedings.pdf
[Malita2 '15] Mihaela Malita, Gheorghe M. Stefan: "From Kleene's Model to the Parallel Abstract Machine", DACS 2015, Bucuresti, June, 2015.
[Malita3 '15]Mihaela Malita, Gheorghe M. Stefan: "Functional Language for Map-Reduce Architecture", ICTEI 2015, Chisinau, May, 2015. ISBN 978-9975-45-377-6
[Malita4 '15] Mihaela Malita, Gheorghe M. Stefan: "MapReduce Accelerator for Embedded Applications", BARC 2015, Boston, January, 2015.
[Goga '16] Nicolae Goga, Mihaela Malita, David Mihaita, Gheorghe M. Stefan: > "FPGA Based Accelerator for Molecular Dynamics", ACSE 2016, Rome, 27-29 July, ISBN: 978-84-944311-8-0
[Stefan '16] Gheorghe M. Stefan, Calin Bira, Radu Hobincu, Mihaela Malita :"FPGA-Based Programmable Accelerator for Hybrid Processing", in ROMJIST, Volume 19, Number 1-2, 2016, pp. 148–165. ISSN 1453-8245
[Bira '16] Calin Bira, Mihaela Malita, Gheorghe M. Stefan: "Functional Virtual Prototyping Environment for a Family of Map-Reduce Embedded Accelerators", in 2016 Third International Conference on Mathematics and Computers in Sciences and in Industry, Chania, Greece August 27-29, pp 155-160. 2016 IEEE DOI 10.1109/MCSI.2016.37
[Mihaita '17] David Mihaita, Gheorghe M. Stefan: "Hybrid Accelerator with MapReduce Architecture for Convolutional Neural Networks" in ROMJIST, Volume 20, Number 3, 2017, pp. 186-197
[Malita '17] Mihaela Malita, Gheorghe M. Stefan: "Map-Scan Node Accelerator for Big-Data", in 2017 IEEE International Conference on Big Data (BIGDATA), 4th Workshop on Advances in Software and Hardware for Big Data to Knowledge Discovery, Dec. 11-14, 2017 @ Boston, MA, USA, pp. 3442-3447. 978-1-5386-2715-0/17/$31.00 ©2017 IEEE. DOI: 10.1109/BigData.2017.8258342
[Mihaita1 '17] David Mihaita, Gheorghe M. Stefan: "Map-Reduce Accelerator for AI", The 40th edition of the INTERNATIONAL SEMICONDUCTOR CONFERENCE, Sinaia, Romania, 11-14 October 2017, pp. 175-178. DOI: 10.1109/SMICND.2017.8101192
[Malita1 '17] Mihaela Malita, David Mihaita, Gheorghe M. Stefan: "Molecular Dynamics on FPGA Based Accelerated Processing Units", Published online: 04 October 2017, DOI: https://doi.org/10.1051/matecconf/201712504012 CSCC 2017, Crete, 14-17 July, DOI: 10.1051/matecconf/20171250
[Andonie '17] Razvan Andonie, Mihaela Malita, Gheorghe M. Stefan: "MapReduce: From Elementary Circuits to Cloud", in Kreinovich, Vladik (Ed.): Uncertainty Modeling, Springer, 2017, pp. 1-14. ISBN 978-3-319-51051-4 DOI: 10.1007/978-3-319-51052-1
[Stefan '18] Gheorghe M. Stefan: "Searching Beyond of the Turing Based Architectures to Surpass the Moore’s Law Challenges" in Advances in micro- and nanoelectronic technology, as number 27 of the series Micro- and nanoengineering edited by the Romanian Academy, pp 23-48.
[Stefan1 '18] Gheorghe M. Stefan, Razvan Mihai : "Driven Distributed Consensus for an Integrated Globalized World", in ROMJIST, Volume 21, Number 2, 2018, pp. 114-128.
[Malita '18] Mihaela Malita, George Vlad Popescu, Gheorghe M. Stefan: "Hybrid System for Deep Learning", in 1st International Conference on Neuroscience, Neuroinformatics, Neurotechnology and Neuro-Psycho- Pharmacology
[Malita1 '18] Mihaela Malita, Gheorghe M. Stefan: "A Recursive Growing & Featuring Mechanism for Nanocomputing Structures", in 14th IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2018) 18-19 July 2018 Athens, Greece, ACM. ISBN 123-4567-24-567/08/06. https://doi.org/10.475/123_4
[Malita2 '18] Mihaela Malita, Octavian Nedescu, Alexandru Negoita, Gheorghe M. Stefan: "Deep Learning in Low-Power Stereo Vision Accelerator for Automotive", in 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, January 12-14, 2018. pp. 473-478 DOI: 10.1109/ICCE.2018.8326285
[Dragomir '19]Voichita Dragomir, Gheorghe M. Stefan: "All-Pair Shortest Path on a Hybrid Map-Rreduce Based Architecture", Proceeding of the Romanian Academy, Series A, Volume 20, Number 4/2019, pp. 411-417
[Malita '19] Mihaela Malita, George Vladut Popescu, Gheorghe M. Stefan: "Heterogenous Computing System for Deep Learning", in Witold Pedrycz, Shyi-Chen (Eds.): Deep Learning: Concepts and Architectures, Springer International Publishing, pp 287-319, 2019. DOI 10.1007/978-3-030-31756-0
[Mihai '19] Razvan Mihai, Tom Einar Nyberg, Einar Michaelsen, Ioana Rizea-Popp, Monica Dascalu, and Gheorghe M. Stefan: "IT-Based Financial Confirmation & Diagnosis Mechanisms", ROMJIST, vol.22, no. 3-4, 2019, pp 284-299.
[Malita1 '19] Mihaela Malita, George Vladut Popescu, Gheorghe M. Stefan: "Heterogenous Computing for Markov Models in Big Data", 2019 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, NV, USA pp. 1500 - 1505 DOI: 10.1109/CSCI49370.2019.00279
[Mihai1 '19] Razvan Mihai, Mihaela Malita, Gheorghe M. Stefan: "Nano-Structural Requirements for Artificial Intelligence & Blockchain Applications" Proceedings of the 42nd International Semiconductor Conference CAS 2019, 9—11 October 2019, Sinaia, Romania, pp 115-118. DOI: 10.1109/SMICND.2019.8923787 At: https://ieeexplore.ieee.org/document/8923787
[Malita '20] Mihaela Malita, George-Vladut Popescu, Gheorghe M. Stefan: "Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral Clustering", 2020 IEEE International Conference on Big Data (IEEE BigData 2020) 10-13 Dec. 2020, virtually, pp 5138-5145.
[Antonescu '20] Mihai Antonescu, Gheorghe M. Stefan: "Multi-Function Scan Circuit", Proceedings of the 43nd International Semiconductor Conference CAS 2020, October 2020, Sinaia, Romania, pp 123-126. DOI: 10.1109/CAS50358.2020.9268048
[Dragomir '20] Voichita Dragomir, Gheorghe M. Stefan: "Sparse Matrix-Vector Multiplication on a Map-Reduce Many-Core Accelerator", ROMJIST, vol.23, no. 3, 2020, pp 262-273.
[Malita1 '20] Mihaela Malita, Razvan Mihai, Gheorghe M. Stefan: "Architectural Features for Artificial Intelligence & Blockchain in the Nano-Era", ROMJIST, vol.23, no. 2, 2020, pp 115-126.
[Malita2 '20] Mihaela Malita, Gheorghe M. Stefan: "Accelerating Clustering. An Architectural Approach", 5th International Conference on Computer and Information Science and Technology (CIST’20), (Prague, Aug.),CIST 103-1:8, 2020. DOI: 10.11159/cist20.103 (https://avestia.com/EECSS2020_Proceedings/files/paper/CIST/CIST_103.pdf)
[Stefan '21] Gheorghe M. Stefan: "Pseudo-Reconfigurable Computing", ROMJIST, vol. 24, no. 4, 2021, pp 366-383.
[Malita '22] Mihaela Malita, Gheorghe M. Stefan: "A Recursive Hierarchy for Accelerator-Level Parallelism", Proceedings of the 8th World Congress on Electrical Engineering and Computer Systems and Sciences (EECSS’22) Prague, Czech Republic - July 28-30, 2022, pp 123-1 - 123-8.
[Malita '23] Mihaela Malita, Gheorghe M. Stefan: "Avoiding Latencies of Log-Depth Parallel Computational Patterns", ISPDC 2023 The 22nd IEEE International Symposium On Parallel And Distributed Computing
[Antonescu '23] Mihai Antonescu, Mihaela Malita, Gheorghe M. Stefan: “Latency Hiding of Log-Depth Scan and Reduce Networks in Heterogeneous Embedded Systems”, Proceeding of the IEEE 29th International Symposium for Design and Technology in Electronic Packaging. , pp 81-86. DOI: 10.1109/SIITME59799.2023.10430611
[Malita '23a] Mihaela Malita, Gheorghe M. Stefan: "In-Memory Parallel Processing for Matrix Transpose", accepted at Rivier Academic Joutnal, vol. 18, no. 1.
[Antonescu '24] Mihai Antonescu, Gheorghe M. Stefan: "Multi-Function Scan Circuit for Assisting the Parallel Computational Map Pattern", ROMJIST, vol. 27, no. 1, 2024, pp 3-20.