/*********************************** VeriLab 1 BEHAVIORAL DESCRIPTIONS IN VERILOG ************************************/ /* Each problem is contained in 'brackets' as follows: */ /* */ /* Modules can be placed in distinct files and put together into a project, one for each problem. Another way is to 'remove' a pair of 'brackets', using //, so activating only one problem and running it right in this file. */ /*************** PROBLEM NO.1: Expandable 8-bit incrementer */ ///* // The module describing the circuit behavior module increment(out, carry, in, inc); input inc; // acive high incrementing command input[7:0] in; // the number to be incremented output carry; // carry output output[7:0] out; assign {carry, out} = in + inc; endmodule // The description of the testing system module test_inc; reg up; // the variable used to command the incrementation reg[7:0] in_variable; // the input variable wire[7:0] out_variable; // the 'connection', of the device to be tested, to the 'monitor' initial begin in_variable = 0; up = 0; #1 in_variable = 8'b100; // after one time unit #1 up = 1'b1; // after another time unit #1 in_variable = 8'd31; // and so on #1 in_variable = 8'b1001101; #1 in_variable = 8'd255; end // 'plug-in' the device under test calling them 'increment_1' increment increment_1(out_variable, carry, in_variable, up); initial begin $display("INCREMNTER'S TESTING"); // displayes the string between brackets $display(" "); // space // monitors the signals listed betwenn brackets $monitor("Time=%0d up=%b in_variable=%b carry=%b out_variable=%b", $time, up, in_variable, increment_1.carry, out_variable); end endmodule //*/ /*************** PROBLEM NO.2: The behavioral description of an 8-bit adder/substractor */ /* module sum_dif(out, carry, in_left, in_right, carry_in, op); input carry_in, // carry input received from the lower binary level op; // op = 0 for add; op = 1 for substract input[7:0] in_left, // left operand in_right; // right operand output carry; // carry output for the next binary order output[7:0] out; // the result reg carry; // variable which takes the value of carry in the procedure 'always' reg[7:0] out; // variable which takes the value of result in the procedure 'always' always @(in_left or in_right or carry_in or op) // always 'in_left' or 'in_right or // 'carry_in' sau 'op' change, the values 'out' and 'carry' are both computed again if (op == 0) {carry, out} = in_left + in_right + carry_in; else {carry, out} = in_left - in_right - carry_in; endmodule module test_sum_dif; reg op, carry_in; reg[7:0] in_left, in_right; wire[7:0] result; initial begin in_left = 0; in_right = 0; carry_in = 1; op = 0; #1 op =1; #1 in_left = 8'b100; in_right = 8'b10; #1 op = 1'b1; #1 op = 0; #1 in_left = 8'd31; in_right = 8'd255; #1 carry_in = 0; end sum_dif modul_1(result, carry, in_left, in_right, carry_in, op); initial begin $display("TESTING"); $display(" "); $monitor("Time=%0d op=%b carry_in=%b in_left=%b in_right=%b carry=%b result=%b", $time, op, carry_in, in_left, in_right, modul_1.carry, result); end endmodule */ /*************** PROBLEM NO.3: A top level structural description of an 8-bit adder/substractor The structure will contains an adder and a circuit that compute 1-complement under the command 'op'. The 2-complement is completed connecting 'op' to the carry input of the adder. */ /* // The main module module plus_min(out, carry, in_left, in_right, op); input op; // 'op = 0' means add and 'op = 1' means substract input[7:0] in_left, // the left operand in_right; // the right operand, the substractor output carry; // means 'borrow' if substract output[7:0] out; wire[7:0] w1; // an 8-bit internal connection inside the module complement module_1(w1, in_right, op); // defined in the next module sum module_2(out, carry, in_left, w1, op); // defined after the next module endmodule // Additional modules called in the main module module complement(out, in, compl); input compl; input[7:0] in; output[7:0] out; reg[7:0] out; always @(in or compl) if (compl) out = ~in; // the 1-complement else out = in; endmodule module sum(out, carry_out, in_1, in_2, carry_in); input carry_in; input[7:0] in_1, in_2; output carry_out; output[7:0] out; assign {carry_out, out} = in_1 + in_2 + carry_in; endmodule // The test module module test_plus_min; reg op; reg[7:0] in_left, in_right; wire[7:0] out; initial begin #1 op = 0; in_left = 8'd5; in_right = 8'd12; #1 op = 1; #1 op = 0; in_left = 8'd255; in_right = 8'd12; #1 op = 1; end plus_min dut(out, carry, in_left, in_right, op); initial begin $display("TESTING THE STRUCTURE OF THE ADDER/SUBSTRACTOR"); $display(" "); $monitor("Time=%0d op=%b in_left=%b in_right=%b carry=%b rezultat=%b", $time, op, in_left, in_right, dut.carry, out); end endmodule */ /*************** PROBLEM NO.4: The structural description of 32-bit incrementer using the module from Problem no.1 */ /* // The main module module inc_32(out, carry, in, inc); input inc; input[31:0] in; output carry; output[31:0] out; wire w1, w2, w3; increment mod_3(out[31:24], carry, in[31:24], w3), mod_2(out[23:16], w3, in[23:16], w2), mod_1(out[15:8], w2, in[15:8], w1), mod_0(out[7:0], w1, in[7:0], inc); // 4 incrementers are instantiated and // interconnected using wires endmodule // The module called four time in the main module (mod_3, ..., mod_0) module increment(out, carry, in, inc); input inc; input[7:0] in; output carry; output[7:0] out; assign {carry, out} = in + inc; endmodule // Testing the 32-bit incrementer module test_inc_32; reg inc; reg[31:0] in; wire[31:0] out; initial begin inc = 0; in = 32'b0; #2 in = 32'b10101; #2 inc = 1; #2 in = 32'd255; #2 in = 32'd65535; #2 in = 32'd16777215; #2 in = 32'd4294967295; end inc_32 dut(out, carry, in, inc); initial begin $display("TESTING THE 32-BIT INCREMENTER"); $display(" "); $monitor("Time=%0d inc=%b in=%b carry=%b out=%b", $time, inc, in, dut.carry, dut.out); end endmodule */ /*************** PROBLEM NO.5: 32-bit adder (to be done by students) */ /* // The main module module sum_32(out, carry_out, carry_in, left_in, right_in); input carry_in; input[31:0] left_in, right_in; output carry_out; output[31:0] out; endmodule */ /*************** PROBLEM NO.6: The n-bit counter */ /* // The main module module counter(out, up, reset, clock); parameter dim = 4; // all the occurences of 'dim' will be replaced with '4' input up, reset, clock; output[dim - 1:0] out; reg[dim - 1:0] out; // contains the current value as the internal state of the counter always @(posedge clock) // at each positive transition of the clock if (reset) out = 0; // the synchronous reset else if (up) out = out + 1; endmodule // The tester module test_counter; parameter dim = 4; reg up, reset, clock; wire[dim - 1:0] out; initial #300 $stop; // the simulation stops after 300 time units initial begin clock = 0; forever #5 clock = ~clock; // the clock signal has the period of 10 time units end initial begin reset = 1; up = 0; #20 reset = 0; #40 up = 1; #200 up = 0; end counter dut(out, up, reset, clock); initial begin $display("TESTING THE 4-BIT COUNTER"); $display(" "); $monitor("Time=%0d clock=%b reset=%b up=%b out=%b", $time, clock, reset, up, dut.out); end initial $vw_dumpvars; // displayes the vawe forms endmodule */ /*************** PROBLEM NO.7: The structural description of the counter */ /* module counter(out, up, reset, clock); `include "parametri.v" // the file 'parametri.v' contains: parameter dim = 4; // and is placed in the same folder with the project input up, reset, clock; output[dim - 1:0] out; wire[dim - 1:0] w1, w2; incrementer inc_1(w2, out, up); selector sel_1(w1, w2, 4'b0, reset); register reg_1(out, w1, clock); endmodule module incrementer(out, in, inc); `include "parametri.v" input inc; input[dim - 1:0] in; output[dim - 1:0] out; assign out = in + inc; endmodule module selector(out, left_in, right_in, sel); `include "parametri.v" input sel; input[dim - 1:0] left_in, right_in; output[dim - 1:0] out; reg[dim - 1:0] out; // means a variable only always @(left_in or right_in or sel) if (sel) out = right_in; else out = left_in; endmodule module register(out, in, clock); `include "parametri.v" input clock; input[dim - 1:0] in; output[dim - 1:0] out; reg[dim - 1:0] out; // means an actual register, not only a variable always @(posedge clock) out = in; endmodule module test_counter; parameter dim = 4; reg up, reset, clock; wire[dim - 1:0] out; initial #300 $stop; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset = 1; up = 0; #20 reset = 0; #40 up = 1; #200 up = 0; end counter dut(out, up, reset, clock); initial begin $display("TESTAREA NUMARATORULUI DE 4 BITI"); $display(" "); $monitor("Time=%0d clock=%b reset=%b up=%b out=%b", $time, clock, reset, up, dut.out); end initial $vw_dumpvars; endmodule */ /*************** PROBLEM NO.8: Up-down counter (to be done) */ /* module rev_counter(out, in, count, up_down, load, reset); `include "parameters.v" input count, // commands counting; has the lowest priority up_down, // commands the counting mode load, // commands the load with the value 'in'; has the second priority reset; // commands the reset; has the highest priority input[dim - 1:0] in; // the value to be loaded in counter output[dim - 1:0] out; endmodule */